module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output reg[23:0] out_bytes,
    output done); //

    reg [1:0] state;
    reg [1:0] next_state;
    reg[23:0] in_bytes;
    parameter b1=0,b2=1,b3=2,bd=3;
    // State transition logic (combinational)
    always @(*) begin
        case (state)
            b1:begin
                if (in[3]==1) begin
                    next_state=b2;
                    in_bytes[23:16]=in;
                end else begin
                    next_state=b1;
                end
            end
            b2:begin
                next_state=b3;
                in_bytes[15:8]=in;
            end
            
            b3:begin
                next_state=bd;
                in_bytes[7:0]=in;
                out_bytes=in_bytes;
            end
            bd:begin
                
                if (in[3]==1) begin
                    next_state=b2;
                    in_bytes[23:16]=in;
                end else begin
                    next_state=b1;
                end                
            end

        endcase
    end

    // State flip-flops (sequential)
    always @(posedge clk ) begin
        if (reset==1) begin
            state<=b1;
        end else begin
            state<=next_state;
        end
    end
    // Output logic
    assign done=(state==bd);


endmodule
